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1 of 13 112006 ds75lv digital thermometer and thermostat www.maxim-ic.com description this low-voltage (1.7v to 3.7v) digital thermometer and thermostat provides 9-, 10-, 11-, or 12-bit digital temperature readings over a -55c to +125c range with 2c accuracy over a -25 c to +100c range. at power-up, the ds75lv defaults to 9-bit resolution for software compatibility with the lm75. communication with the ds75lv is achieved through a simple 2-wire serial interface. three address pins allow up to eight ds75lv devices to operate on the same 2-wire bus, which greatly simplifies distributed temperature- sensing applications. the ds75lv thermostat has a dedicated open-drain output (o.s.) and programmable fault tolerance, which allows the user to define the number of consecutive error conditions that must occur before o.s is activated. there are two thermostatic operating modes that cont rol thermostat operation based on user-defined trip-points (t os and t hyst ). a block diagram of the ds75lv is shown in figure 1 and detailed pin descriptions are given in table 1. applications personal computers cellular base stations office equipment any thermally sensitive system pin configuration features ? operating range from 1.7v to 3.7v ? temperature measurements require no external components ? measures temperatures from -55c to +125c (-67f to +257f) ? 2c accuracy over a -25c to +100c range ? thermometer resolution is user- configurable from 9 (default) to 12 bits (0.5 c to 0.0625 c resolution) ? 9-bit conversion time is 25ms (max) ? thermostatic settings are user-definable ? data read/write occurs through a 2-wire serial interface (sda and scl pins) ? data lines filtered internally for noise immunity (50ns deglitch) ? bus timeout feature prevents lockup problems on 2-wire interface ? multidrop capability simplifies distributed temperature-sensing applications ? pin/software compatible with the lm75 ? available in 8-pin sop ( max) and so packages ordering information part temp range pin-package ds75lvs+ -55c to +125c ds75lv (150-mil) 8-so ds75lvs+t&r -55c to +125c ds75lv (150-mil) 8-so, 2500 piece tape-and-reel ds75lvu+ -55c to +125c ds75lv 8-sop (max) ds75lvu+t&r -55c to +125c ds75lv 8-sop (max), 3000 piece tape- and-reel ordering information continued at the end of the data sheet. ds75lvs?so ( 150 mils) sc l v dd a 0 a 1 a 2 gnd o.s. s d a 6 8 7 5 3 1 2 4 ds75l sc l v dd a 0 a 1 a 2 gnd o.s. s d a 6 8 7 5 3 1 2 4 ds75l ds75lvu? sop/ max
ds75lv: digital thermometer and thermostat 2 of 13 absolute maxi mum ratings* voltage on v dd , relative to ground -0.3v to +4.0v voltage on any other pin, relative to ground -0.3v to +6.0v operating temperature range -55 c to +125 c storage temperature range -55 c to +125 c soldering temperature 260 c for 10 seconds these are stress ratings only and functional operation of the devic e at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating co nditions for extended periods of time may affect reliability. the dallas semiconductor ds75lv is built to the high est quality standards and manufactured for long-term reliability. all dallas semiconductor devices are made using the same quality materials and manufacturing methods. however, the ds75lv is not exposed to environmental stresses, such as burn-in, that some industrial applications require. for specific reliability information on this product, please contact the factory in dallas at (972) 371-4448. dc electrical characteristics (-55c to +125c; 1.7v v dd 3.7v.) parameter symbol conditions min max units supply voltage v dd (note 10) 1.7 3.7 v -25 to +100 2.0 thermometer error (note 2) t err -55 to +125 3.0 c input logic high v ih (note 1) 0.7 v dd 5.5 v input logic low v il (note 1) -0.5 0.3 v dd v v ol1 3ma sink current 0 0.4 sda output logic low voltage (note 1) v ol2 6ma sink current 0 0.6 v o.s. saturation voltage v ol 4ma sink current (notes 1, 2) 0.8 v input current each i/o pin 0.4 < v i/o < 0.9 v dd -10 +10 a i/o capacitance c i/o 10 pf standby current i dd1 (notes 3, 4) 2 a active temp conversions 1000 active current (notes 3, 4) i dd communication only 100 a ac electrical characteristics (-55c to +125c; 1.7v v dd 3.7v.) parameter symbol condition min typ max units resolution 9 12 bits 9-bit conversions 25 10-bit conversions 50 11-bit conversions 100 temperature conversion time t convt 12-bit conversions 200 ms scl frequency f scl 400 khz bus free time between a stop and start condition t buf (note 5) 1.3 s start and repeated start hold time from t hd:sta (notes 5, 6) 600 ns
ds75lv: digital thermometer and thermostat 3 of 13 falling scl low period of scl t low (note 5) 1.3 s high period of scl t high (note 5) 0.6 s repeated start condition setup time to rising scl t su:sta (note 5) 600 ns data-out hold time from falling scl t hd:dat (notes 5, 8) 0 0.9 s data-in setup time to rising scl t su:dat (note 5) 100 ns rise time of sda and scl (receive) t r (notes 5, 7) 20 + 0.1c b 300 ns fall time of sda and scl (receive) t f (notes 5, 7) 20 + 0.1c b 300 ns spike suppression filter time (deglitch filter) t ss 0 50 ns stop setup time to rising scl t su:sto (note 5) 600 ns capacitive load for each bus line c b 400 pf input capacitance c i 5 pf serial interface reset time t timeout sda time low (note 9) 75 325 ms note 1: all voltages are referenced to ground. note 2: internal heating caused by o.s. loading will cause the ds75lv to read approximately 0.5 c higher if o.s. is sinking the max rated current. note 3: i dd specified with o.s. pin open. note 4: i dd specified with v dd at 3.0v and sda, scl = 3.0v, 0 c to 70 c. note 5: see timing diagram in figure 2. a ll timing is referenced to 0.9 x v dd and 0.1 x v dd . note 6: after this period, the first clock pulse is generated. note 7: for example, if c b = 300pf, then t r [min] = t f [min] = 50ns. note 8: the ds75lv provides an internal hold time of at least 75ns on the sda signal to bridge the undefined region of scl's falling ed ge. note 9: this time-out applies only when the ds75lv is holding sda low. other devices can hold sda low indefinitely and the ds75lv will not reset. note 10: the ds75lv has a maximum operating voltage of 3.7v. contact dalla s semiconductor for information on the availability of a 3.7v to 5.5v version of the ds75lv. table 1. detailed pin description pin symbol pin description 1 sda data input/output . for 2-wire serial communication port. open-drain. 2 scl clock input . 2-wire serial communication port. 3 o.s. thermostat output . open-drain. 4 gnd ground 5 a 2 address input 6 a 1 address input 7 a 0 address input 8 v dd supply voltage. +1.7v to +3.7v supply pin.
ds75lv: digital thermometer and thermostat figure 1. ds75lv func tional block diagram 4 of 13 t os and t hyst re g i s ter s configuration re g i s ter temperature re g i s ter oversampling m o d u lat o r precision referen c e digital de c imat o r address and i/o control a 1 a 2 a 0 figure 2. timing diagram scl sd a v dd gnd thermostat co mparat o r r p o.s.
ds75lv: digital thermometer and thermostat operation ? measuring temperature the ds75lv measures temperature using a bandgap temper ature sensing architecture. an on-board delta-sigma analog-to-digital converter (adc) converts the measured temperature to a digital value that is calibrated in degrees centigrade; for fahrenheit applications a lookup table or conversion routine must be us ed. the ds75lv is factory- calibrated and requires no external co mponents to measure temperature. at power-up the ds75lv immediately begins converting temper ature to a digital value. the resolution of the digital output data is user-configurable to 9, 10, 11, or 12 bits, corresponding to temperature increments of 0.5 c, 0.25 c, 0.125 c, and 0.0625 c, respectively, with 9-bit default resolution at power-up. the resolution is controlled via the r0 and r1 bits in the configuration register as explained in the configuration register section of this data sheet. note that the conversion time doubles for each additional bit of resolution. after each temperature measurement and analog-to-digital conversion, the ds75lv stores the temperature as a 16-bit two?s complement number in the 2-byte temperature register (see figure 3). the sign bit (s) indicates if the temperature is positive or negative: for positive numbers s = 0 and for negative numbers s = 1. the most recently converted digital measurement can be read from the te mperature register at any time. since temperature conversions are performed in the background, reading t he temperature register does not affect the operation in progress. bits 3 through 0 of the temperature register are hard wired to 0. when the ds75lv is configured for 12-bit resolution, the 12 msbs (bits 15 through 4) of the temperat ure register will contain temperature data. for 11-bit resolution, the 11 msbs (bits 15 through 5) of the temperature register will contain data, and bit 4 will read out as 0. likewise, for 10-bit resolution, the 10 msbs (bits 15 through 6) will contain data, and for 9-bit the 9 msbs (bits 15 through 7) will contain data, and all unused lsbs will contai n 0s. table 2 gives examples of 12-bit resolution digital output data and the corresponding temperatures. figure 3. temperature, t os , and t hyst register format bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ms byte s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ls byte 2 -1 2 -2 2 -3 2 -4 0 0 0 0 table 2. 12-bit resolution te mperature/data relationship temperature ( c) digital output (binary) digital output (hex) +125 0111 1101 0000 0000 7d00h +25.0625 0001 1001 0001 0000 1910h +10.125 0000 1010 0010 0000 0a20h +0.5 0000 0000 1000 0000 0080h 0 0000 0000 0000 0000 0000h -0.5 1111 1111 1000 0000 ff80h -10.125 1111 0101 1110 0000 f5e0h -25.0625 1110 0110 1111 0000 e6f0h -55 1100 1001 0000 0000 c900h shutdown mode 5 of 13 for power-sensitive applications, the ds75lv offers a low-power shutdown mo de. the sd bit in the configuration register controls shutdown mode. when sd is changed to 1, the conversion in progress will be completed and the result stored in the temperature regist er after which the ds75lv will go into a low-power standby state. the o.s. output will be cleared if the t hermostat is operating in interrupt mode and o.s will remain unchanged in comparator mode. the 2-wire interface remains operational in shutdown mode, and writing a 0 to the sd bit returns the ds75lv to normal operation.
ds75lv: digital thermometer and thermostat 6 of 13 operation ? thermostat the ds75lv thermostat has two operating modes, co mparator mode and interrupt mode, which activate and deactivate the open-drain thermo stat output (o.s.) based on us er-programmable trip-points (t os and t hyst ). the ds75lv powers up with the thermostat in comparator mode, active-low o.s. polarity, over-temperature trip-point (t os ) register set to 80c, and t he hysteresis trip-point (t hyst ) register set to 75oc. if these power-up settings are compatible with the application, the ds75lv can be used as a standalone thermostat (i.e., no 2?wire communication required). if interrupt mode operati on, active-high o.s. polarity or different t os and t hyst values are desired, they must be programmed after power- up, so standalone operation is not possible. in both operating modes, the user can program the thermost at fault tolerance, which sets how many consecutive temperature readings (1, 2, 4, or 6) must fall outside of the thermostat limits befor e the thermostat output is triggered. the fault tolerance is set by the f1 and f0 bi ts in the configuration register. at power-up the fault tolerance is set to 1. the data format of the t os and t hyst registers is identical to that of the te mperature register (see figure 3), i.e., a two-byte two?s complement representation of the trip-point temperature in degr ees centigrade with bits 3 through 0 hardwired to 0. after every temperature conversion, the measurement is compared to the values stored in the t os and t hyst registers. the o.s. output is u pdated based on the result of the comparison and the operating mode of the ic. the number of t os and t hyst bits used during the thermostat co mparison is equal to the conversion resolution set by the r1 and r0 bits in the configuration regi ster. for example, if the resolution is 9 bits, only the 9 msbs of t os and t hyst will be used by the thermostat comparator. the active state of the o.s. output can be changed via the pol bit in the configuration regi ster. the power-up default is active low. if the user does not wish to use the thermostat capab ilities of the ds75lv, the o.s. output should be left floating. note that if the thermo stat is not used, the t os and t hyst registers can be used for gene ral storage of system data. comparator mode: when the thermostat is in comparator mode, o.s. can be programmed to operate with any amount of hystoresis. the o.s. output becomes acti ve when the measured temperature exceeds the t os value a consecutive number of times as defined by the f1 and f0 faul t tolerance (ft) bits in the configuration register. o.s. then stays active until the first time the tem perature falls below the value stored in t hyst . putting the device into shutdown mode does not clear o.s. in comparator mode. thermostat compar ator mode operation with ft = 2 is illustrated in figure 4. interrupt mode: in interrupt mode, the o.s. output first become s active when the measured temperature exceeds the t os value a consecutive number of times equal to the ft va lue in the configuration register. once activated, o.s. can only be cleared by either putting the ds75lv in to shutdown mode or by reading from any register (temperature, configuration, t os , or t hyst ) on the device. once o.s. has b een deactivated, it will only be reactivated when the measured temperature falls below the t hyst value a consecutive number of times equal to the ft value. again, o.s can only be cleared by putting the dev ice into shutdown mode or reading any register. thus, this interrupt/clear process is cyclical between t os and t hyst events (i.e, t os , clear, t hyst , clear, t os , clear, t hyst , clear, etc.). thermostat inte rrupt mode operation with ft = 2 is illustrated in figure 4.
ds75lv: digital thermometer and thermostat figure 4. o.s. output operation example 7 of 13 configuration register the configuration register allows the user to progra m various ds75lv options such as conversion resolution, thermostat fault tolerance, thermostat polarity, thermostat operating mode, and shutdown mode. the configuration register is arranged as shown in figure 5 and detailed descri ptions of each bit are provided in table 3. the user has read/write access to all bits in t he configuration register except the ms b, which is a reserved read-only bit. the entire register is volatile, and thus powers?up in its default state. figure 5. configuration register msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb 0 r1 r0 f1 f0 pol tm sd in this example the ds75lv is configured to have a fault tolerance of 2. o.s. output - comparator mode conversions inactive active temperature t os t hyst inactive active o.s. output - interrupt mode assumes a read has occurred
ds75lv: digital thermometer and thermostat 8 of 13 table 3. configuration re gister bit descriptions bit name functional description 0 reserved power-up state = 0 the master can write to this bit, but it will always read out as a 0. r1 conversion resolution bit 1 power-up state = 0 sets conversion resolution (see table 4) r0 conversion resolution bit 0 power-up state = 0 sets conversion resolution (see table 4) f1 thermostat fault tolerance bit 1 power-up state = 0 sets the thermostat fault tolerance (see table 5). f0 thermostat fault tolerance bit 0 power-up state = 0 sets the thermostat fault tolerance (see table 5). pol thermostat output (o.s.) polarity power-up state = 0 pol = 0 ? o.s. is active low. pol = 1 ? o.s. is active high. tm thermostat operating mode power-up state = 0 tm = 0 ? comparator mode. tm = 1 ? interrupt mode. see the operation?thermostat section for a detailed description of these modes. sd shutdown power-up state = 0 sd = 0 ? active conversion and thermostat operation. sd = 1 ? shutdown mode. see the shutdown mode section for a detailed description of this mode. table 4. resolution configuration r1 r0 thermometer resolution max conversion time 0 0 9-bit 25ms 0 1 10-bit 50ms 1 0 11-bit 100ms 1 1 12-bit 200ms table 5. fault tolerance configuration f1 f0 consecutive out-of-limits conversions to trigger o.s. 0 0 1 0 1 2 1 0 4 1 1 6
ds75lv: digital thermometer and thermostat 9 of 13 register pointer the four ds75lv registers each have a unique two-bit point er designation, which is defined in table 6. when reading from or writing to the ds75lv, the user must ?point ? the ds75lv to the register that is to be accessed. when reading from the ds75lv, once the pointer is set, it will remain pointed at the same register until it is changed. for example, if the user de sires to perform consecutive reads fr om the temperature register, then the pointer only has to be set to the temperature register one time, after which all reads will automatically be from the temperature register until the pointer value is changed. when writing to the ds75lv, the pointer value must be refreshed each time a write is performed, even if the sa me register is being written to twice in a row. at power-up, the pointer defaults to the temperature register location. t he temperature register can be read immediately without resetting the pointer. changes to the pointer setting are accomplished as described in the 2-wire serial data bus section of this data sheet. table 6. pointer definition register p1 p0 temperature 0 0 configuration 0 1 t hyst 1 0 t os 1 1 2-wire serial data bus the ds75lv communicates over a standard bi-directional 2-wi re serial data bus that consists of a serial clock (scl) signal and serial data (sda) signal. the ds75lv interf aces to the bus via the sc l input pin and open-drain sda i/o pin. all communication is msb first. the following terminology is used to describe 2-wire communication: master device: microprocessor/microcontroller that controls th e slave devices on the bus. the master device generates the scl signal and start and stop conditions. slave: all devices on the bus other than the master . the ds75lv always functions as a slave. bus idle or not busy: both sda and scl remain high. sda is held high by a pullup resistor when the bus is idle, and scl must either be forced high by the master (if the scl output is push-pull) or pulled high by a pullup resistor (if the scl output is open-drain). transmitter: a device (master or slave) that is sending data on the bus. receiver: a device (master or slave) that is receiving data from the bus. start condition: signal generated by the master to indicate the beginning of a data transfer on the bus. the master generates a start condition by pulling sda fr om high to low while scl is high (see figure 6). a ?repeated? start is sometimes used at the end of a data tran sfer (instead of a stop) to indicate that the master will perform another operation. stop condition: signal generated by the master to indicate th e end of a data transfer on the bus. the master generates a stop condition by transitioning sda from low to high while scl is high (see figure 6). after the stop is issued, the master releases the bus to its idle state. acknowledge (ack): when a device (either master or slave) is acting as a receiver, it must generate an acknowledge (ack) on the sda line after receiving every by te of data. the receiving device performs an ack by pulling the sda line low for an entire scl period (see figur e 6). during the ack clock cycle, the transmitting device must release sda. a variation on the ack signal is the ?not acknowledge? (nack). when the master device is acting as a receiver, it uses a nack instead of an ack a fter the last data byte to indicate that it is finished receiving data. the master indicates a nack by le aving the sda line high during the ack clock cycle. slave address: every slave device on the bus has a unique 7-bit address that allows the master to access that device. the ds75lv?s 7-bit bus address is 1 0 0 1 a 2 a 1 a 0 , where a 2 , a 1 and a 0 are user-selectable via the corresponding input pins. the three address pins allow up to eight ds75lvs to be multi-dropped on the same bus.
ds75lv: digital thermometer and thermostat address byte: the control byte is transmitted by the master and consists of the 7-bit slave address plus a read/write (r/w ) bit (see figure 7). if the master is going to read data from the slave device then r/w = 1, and if the master is going to write data to the slave device then r/w = 0. pointer byte: the pointer byte is used by the master to tell th e ds75lv which register is going to be accessed during communication. the six msbs of the pointer byte (see figure 8) are always 0 and the two lsbs correspond to the desired register as shown in table 6. figure 6. start, stop, and ack signals figure 7. address byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 0 0 1 a 2 a 1 a 0 r/w figure 8. pointer byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 0 0 p1 p0 scl sda start condition stop condition ? ? ack (or nack) from receiver general 2-wire information ? all data is transmitted msb first over the 2-wire bus. ? one bit of data is transmitted on the 2-wire bus each scl period. ? a pullup resistor is required on the sda line and, when the bus is idle, both sda and scl must remain in a logic- high state. ? all bus communication must be initiated with a start condition and terminated with a stop condition. during a start or stop is the only time sda is allowed to change states while scl is high. at all other times, changes on the sda line can only occur when scl is low: sda must remain stable when scl is high. ? after every 8-bit (1-byte) transfer, the receiving devic e must answer with an ack (or nack), which takes one scl period. therefore, nine clocks are r equired for every one-byte data transfer. writing to the ds75lv ? to write to the ds75lv, the master must generate a start followed by an address byte containing the ds75lv bus address. the value of the r/w bit must be a 0, which indicates that a write is about to take place. the ds75lv will respond with an ack after receiving the address byte. the master then sends a pointer byte which tells the ds75lv which register is being written to. the ds75lv will again respond with an ack after receiving the pointer byte. following this ack the master device must immediately begin transmitting data to the ds75lv. when writing to the configuration register, the master mu st send one byte of data (see figure 9b), and when writing to the t os or t hyst registers the master must send two bytes of data (see figure 9c). after receiving each data byte, the ds75lv will respond with an ack, and the transaction is finished with a stop from the master. 10 of 13
ds75lv: digital thermometer and thermostat 11 of 13 software por ?the soft power on reset (por) command is 54h. the master sends a start followed by an address byte containing the ds75lv bus address. the r/w bit must be a 0. the ds75lv will respond with an ack. if the next byte is a 0x54, t he ds75lv will reset as if power had been cy cled. no ack will be send by the ic after the por command is received. reading from the ds75lv ?when reading from the ds75lv, if the pointer was already pointed to the desired register during a previous transaction, the read can be performed immediately without changing the pointer setting. in this case the master sends a start followed by an address byte containing t he ds75lv bus address. the r/w bit must be a 1, which tells the ds 75lv that a read is being performed. after the ds75lv sends an ack in response to the address byte, the ds 75lv will begin transmitting the requested data on the next clock cycle. when reading from the configuration register, the ds75lv will tr ansmit one byte of data, after which the master must respond with a nack followed by a stop (see figure 9e ). for two-byte reads (i.e., from the temperature, t os or t hyst register), the ds75lv will transmit tw o bytes of data, and the master must respond to the first data byte with an ack and to the second byte with a nack followed by a stop (see figure 9a). if only the most significant byte of data is needed, the master can issue a nack followed by a stop after reading the first data byte in which case the transaction will be the same as for a read from the configuration register. if the pointer is not already pointing to the desired register , the pointer must first be updated as shown in figure 9d, which shows a pointer update followed by a single-byte read. the value of the r/w bit in the initial address byte is a 0 (?write?) since the master is going to write a pointer byte to the ds75lv. after the ds75lv responds to the address byte with an ack, the master sends a pointer byte that corresponds to the desired register. the master must then perform a repeated start followed by a stan dard one or two byte read sequence (with r/w =1) as described in the previous paragraph. bus timeout ?the ds75lv has a bus timeout featur e that prevents communication errors from leaving the ic in a state where sda is held low disrupting ot her devices on the bus. if the ds75lv holds the sda line low for a period of t timeout , its bus interface will automatica lly reset and release th e sda line. bus communi cation frequency must be fast enough to prevent a reset during normal operat ion. the bus timeout feature only applies to when the ds75lv is holding sda low. other devices can hold sda low for an undefined period without causing the interface to reset.
ds75lv: digital thermometer and thermostat figure 9. 2-wire interface timing (ds75lv) (ds75lv) a d2 d6 d5 d4 d3 d1 d0 a0 wa a1 0 00 0 0 00 1ad7 a2 b) write to the configuration register s1 1 00 address byte start scl sda ack pointer byte p data byte (from master) stop ack ack (ds75lv) (ds75lv) (ds75lv) a d2 d6 d5 d4 d3 d1 d0 a0 wa a1 0 00 0 0 00 1 0 00 0 0 00 1ad7 a2 b) write to the configuration register s1 1 00 address byte start scl sda ack pointer byte p data byte (from master) stop ack ack (ds75lv) c) write to the t os or t hyst register a2 a1 a0 scl sda s 1 1 0 0 w a address byte start ack (ds75lv) a 0 0 000 0 p1 p0 pointer byte ack (ds75lv) d4 d6 d5 d3 d2 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 a d1 p ls data byte (from master) a ms data byte (from master) stop ack (ds75lv) ack (ds75lv) c) write to the t os or t hyst register a2 a1 a0 scl sda s 1 1 0 0 w a address byte start ack (ds75lv) a 0 0 000 0 p1 p0 0 0 000 0 p1 p0 pointer byte ack (ds75lv) d4 d6 d5 d3 d2 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 a d1 p ls data byte (from master) a ms data byte (from master) stop ack (ds75lv) ack (ds75lv) d) read single byte (new pointer location) (ds75lv) start (from ds75lv) (master) (ds75lv ) (ds75lv) n a 0 s1 1 0 0 a2 a1 a0 w 0 00 a 0 0 d6 d5 d4 d3 d2 d1 d0 p d7 s1 1 00 a2 a1 a0 ra ack repeat scl sda address byte start pointer byte data byte stop nack address byte ack ack p1 p0 n a 0 s1 1 0 0 a2 a1 a0 w 0 00 a 0 0 d6 d5 d4 d3 d2 d1 d0 p d7 s1 1 00 a2 a1 a0 ra ack repeat scl sda address byte start pointer byte data byte stop nack address byte ack ack p1 p0 p1 p0 s e) read from the configuration register (current pointer location) scl sda start n d6 d5 d4 d3 d2 d1 d0 p d7 1 1 00 a2 a1 a0 ra data byte (from ds75lv) stop nack (master) address byte ack (ds75lv) s e) read from the configuration register (current pointer location) scl sda start n d6 d5 d4 d3 d2 d1 d0 p d7 1 1 00 a2 a1 a0 ra data byte (from ds75lv) stop nack (master) address byte ack (ds75lv) n d6 d5 d4 d3 d2 d1 d0 p d7 1 1 00 a2 a1 a0 ra data byte (from ds75lv) stop nack (master) address byte ack (ds75lv) s a) read 2-bytes from the temperature, t os or t hyst register (current pointer location) scl sda start a d6 d5 d4 d3 d2 d1 d0 d7 1 1 0 0 a2 a1 a0 ra ms data byte (from ds75lv) ack (master) address byte ack (ds75lv) n d6 d5 d4 d3 d2 d1 d0 p d7 ls data byte (from ds75lv) stop nack (master) s a) read 2-bytes from the temperature, t os or t hyst register (current pointer location) scl sda start a d6 d5 d4 d3 d2 d1 d0 d7 1 1 0 0 a2 a1 a0 ra ms data byte (from ds75lv) ack (master) address byte ack (ds75lv) n d6 d5 d4 d3 d2 d1 d0 p d7 ls data byte (from ds75lv) stop nack (master) 12 of 13
ds75lv: digital thermometer and thermostat 13 of 13 ordering information part temp range package marking pin-package ds75lvs+ -55c to +125c ds75l* ds75lv (150-mil) 8-so ds75lvs+t&r -55c to +125c ds75l* ds75lv (150-mil) 8-so, 2500 piece tape-and-reel ds75lvu+ -55c to +125c ds75l** ds75lv 8-sop (max) ds75lvu+t& r -55c to +125c ds75l** ds75lv 8-sop (max), 3000 piece tape-and-reel ds75lvs -55c to +125c ds75l ds75lv (150-mil) 8-so ds75lvs/t&r -55c to +125c ds75l ds75lv ( 150-mil) 8-so, 2500 piece tape-and-reel ds75lvu -55c to +125c ds75l ds75lv 8-sop (max) ds75lvu/t&r -55c to +125c ds75l ds75lv 8-sop (max), 3000 piece tape-and-reel * a ?+? symbol is also marked on t he package near the pin 1 indicator. **the ds75lv has a maximum operating voltage of 3.7v. contact da llas semiconductor for information on the availability of a 3.7 v to 5.5v version of the ds75lv. package information (for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .)

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